NAND Gate Experiment
Student Information
Name of Student:
Year and Section:
Date Performed:
Part 1. Objectives
To verify experimentally the proper operation of a **NAND gate**.
To use a **NAND gate as an inverter**.
To demonstrate that the **NAND gate is a universal gate**.
Part 2. Equipment and parts required:
1 triple 3 – input NAND gate, '10
1 power supply, 5V DC
1 VOM
Part 3. Procedure
1. Record here the exact device you are using.
2. Examine the data sheet for a **'10 IC**. Note the value of Vcc required and the maximum required supply current Icc
Vcc:
Icc:
3. Apply power to the '10 proper operation of one of the 3 – input gates by measuring the output voltage level for each of the eight input – signal combinations shown in Fig. 1 Use input voltage levels of 0 = 0V dc, 1 = +5 V dc, and use the measure output voltage levels to complete the truth table below.
A
B
C
x
0
0
0
+5
0
0
0
+5
0
+5
+5
0
0
0
+5
+5
0
+5
0
+5
+5
+5
+5
+5
4. Connect the 3 inputs on one of the gates together so it can be used as an inverter. Verify that the gates operates as an inverter by applying 0 V dc, and then +5 V dc to the input and recording outputs.
A
x
0 V dc
+5 V dc
5. Determine whether or not a 3 - input NAND gate will function as an inverter if 2 of the inputs are left unconnected and the third is used as a single output
6. Connect two of the NAND gates shown in Fig 2, and complete the truth table below to verify operation as an OR function.
A
B
Output
0
0
0
+5
+5
0
+5
+5
7. Connect three of the NAND gates shown in Fig 2, and complete the truth table below to verify operation as an OR function.
A
B
x
0
0
0
+5
+5
0
+5
+5
Part 5. Questions
1. A '10 NAND gate is to be used as a 2 - input NAND gate. What could you do with the extra input?
2. Explain what is meant by a fanout of 8.
3. Using the result from step 5, explain whether or not a '10 NAND gate will function as an inverter if the unused inputs are left unconnected.
4. Explain why NAND gate is considered to be a universal gate.
5. A certain logic network requires three inverters, two 3 - input AND gates, and one 2 - input OR gate. If the realization is to be accomplished using only '10 NAND gates, what is the minimum number of **'10s** required? Draw the logic diagram for each type of realization.
6. Draw a logic diagram showing how to get the OR function x = A + B + C using NAND gates assuming all the functions and their complements are available.
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