In the domain of digital circuit design, the simplification of logic functions stands as a critical endeavor. Initial Boolean expressions, while accurately representing circuit behavior, frequently contain redundancies that translate into inefficient hardware implementations. Such inefficiencies manifest as an increased requirement for logic gates, higher power consumption, and consequently, elevated manufacturing costs. Therefore, the application of systematic algebraic manipulations and graphical methods for the simplification of these Boolean expressions is imperative. This optimization process yields functionally equivalent yet more parsimonious circuit realizations, directly contributing to enhanced performance, reduced resource utilization, and improved overall viability of digital systems, from microprocessors to embedded electronic applications.